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A sneak peek at chips of the future


What IS IEDM? IEDM stands for the World Electron Units Assembly, and it’s THE global discussion board for nanoscale device technology. Papers at this discussion board characterize the “easiest-of-the-absolute best” in device accomplishments for the calendar year. 1400 folks attended the convention, with an acceptance charge for papers of ~35% (and that features the invited papers!) The discussion board oscillates in place between San Francisco and Washington DC, and this year it used to be in Washington DC.

One of the most first impressions one will get in attending IEDM is how so much Intel is held up because the “goal to beat”. This used to be in particular obvious in session 9 (Circuit and Software Interplay – Evolved CMOS Expertise Systems) the place the foremost avid gamers within the trade now not best benchmarked their information towards ours, however even used equivalent portraits and structure as our displays. (The quote “Imitation is probably the most honest type of flattery” springs to thoughts on this discussion board!) An excellent instance used to be TSMC’s 16nm FinFET paper, which was once benchmarked (just about graph for graph) in opposition to our 22nm technology (VLSI 2012, Chris Auth, et al. and IEDM 2012, Chia-Hong Jan, et al.).

Some other interesting factor about session 9 used to be the growing emphasis on elements of the gadget past the device itself. Intel, as an example, offered an extraordinarily smartly-got paper (Eric Wang, et al.) on a capacitor-over-bitline eDRAM carried out on 22nm Trigate (see Fig. 1). Eric, the principle writer, did a pleasant job in shifting past the device to center of attention on device-circuit interactions, displaying that implementation of noise discount circuit tactics and intensive device and design co-optimization may supply over one hundredμs retention time at ninety five°C in a Gbit eDRAM. (This paper additionally confirmed probably the most traits of Intel papers at IEDM, which is for the room to dramatically refill with individuals ahead of an Intel paper, after which empty once more after the paper is finished.)


Fig. 1. The Capacitor-over-bitline (COB) eDRAM architecture discussed in Eric Wang’s session 9 Intel paper.

Device-circuit interactions were also the theme of the Intel invited paper (Greg Taylor) which led off session 17 (Circuit and Device Interaction – Analog and Mixed Signal Circuit/Device Interactions). Greg discussed the challenges of implementing analog and mixed signal circuits on process technologies that have been optimized for logic performance (always a hot button in this community!). One of the points he made was the importance of moving as much circuitry as possible to the logic device and focusing device development energy only on those devices/circuits which cannot be made using logic. Greg also pointed out the possibilities for leveraging challenges as benefits (something I instantly named “Aikido Analog”) and gave an example of an analog to digital converter that benefits from increased device variation.

Intel had a very strong presence this year in the novel devices community, with two well-received papers on tunnel FETs (TFETs) and a fascinating paper on some fundamental science in GaN devices.

TFETs are electron devices which operate by tunneling through the source-drain energy barrier (rather than by hopping over the barrier as in a conventional MOS device.) As a consequence of using tunneling, they have better sub-threshold slope than MOS, and thus a potential for better performance at low energy/power operating points. Intel had two TFET papers this year, one in session 4 (Nano Device Technology – Steep Slope Devices) and one in session 33 (Circuit and Device Interaction – Circuit/Device Variability and Reliability). In the Session 4 paper (Uygar Avci and Ian Young), Uygar introduced an innovative new device (called a resonant tunnel FET) which creates a narrow triangular potential well at the source side of the heterojunction possessing discrete resonant energy levels. If these resonant levels can be designed to align with the source valence band when the device is on, then a significantly steeper subthreshold stope can be obtained (see Fig. 2). In the session 33 paper (Uygar Avci, et al.), Uygar discussed the impact of variations on TFET devices when compared to conventional MOS devices, and predicted a 64% average energy savings against Si CMOS at Lg=13nm.


Fig. 2. Development of the resonant tunnel TFET over a standard TFET and MOS device as proven in Uygar Avci’s session four Intel paper.

It’s uncommon in our industry so that you can exhibit totally new physics to the transistor neighborhood. Alternatively, this year, we had been a success with a paper in session 28 (Energy and Compound Semiconductor Gadgets – Subsequent technology common sense and energy). On this paper (H. Then, et al.) Han mentioned the remark of a “terrible capacitance” impact in an AlInN/AlN/GaN MOS-HEMT. He brought up that terrible capacitance results (fascinating to us as a result of they lead to stronger subthreshold efficiency, just like a TFET) had been expected theoretically, however now not within the GaN gadget and now not with this specific kind of physics. That you could think about that the query duration for this paper used to be reasonably energetic, with quite a lot of physics specialists torn between disagreeing with our interpretation however being impressed and intrigued with the aid of our information!

Remaining, however in no way least, have been the panel classes. Intel’s Kevin Zhang chaired the session on “Will Voltage Scaling in CMOS Expertise Proceed Past the 14nm Era?” and I was once one of the vital panelists. I will undoubtedly say that Kevin’s session was once a thrilling one, starting with the dramatic concept by means of IBM’s Tak Ning for a return to bipolar and ending with my (almost definitely much less dramatic, however possible extra sensible) statement that design-course of collaboration appears to be the important thing for CMOS scaling earlier 14nm IBM’s Jeff Welser chaired the session on “Is there existence past typical CMOS” and Ian Younger was once one of the vital panelists. On this session, panelists each proposed the steep slope (Tunneling FET, Ferro-electrical FET, Metallic Insulator FET) devices and the spintronics devices (All-Spin Common sense) because the probably entrance runner devices past typical CMOS. A few panelists mentioned these devices should present energy-efficiency merit on the practical block and device degree, the place Past CMOS devices won’t change CMOS however will increase it (i.e. “Past CMOS” will “Be-On-CMOS”). Ian made the purpose that a brand new device could most effective happen if it permits new functions – now not simply be about changing CMOS. One sturdy possibility for that is heterogeneous integration of CMOS and Past CMOS devices to extra optimally put into effect the capabilities within the SOC.

General, the convention “development” used to be upbeat – with quite a lot of vitality showcasing applied sciences of price to the mobile and SOC communities. Nonetheless no lead to sight for Moore’s Legislation!